Video processing apparatus and method for allocating addresses to data of macroblocks and storing the same, and medium containing a program for performing such method

ABSTRACT

One macroblock is constructed by 16×16 pixels (bytes). When the macroblocks are stored in a frame memory constructed by a DRAM or the like, addresses are sequentially allocated in an ascending order in a manner such that addresses  0000  to  0255  are allocated to the first macroblock and addresses  0256  to  0512  are allocated to the second macroblock and the macroblocks are stored. The macroblocks stored in this manner are read out in the ascending order of the addresses.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.09/719,452 filed Feb. 26, 2001, the disclosure of which is herebyincorporated herein by reference, which is a 371 of PCT/JP00/02406 filedApr. 13, 2000.

TECHNICAL FIELD

The invention relates to video processing apparatus and method and amedium and, more particularly, to video processing apparatus and methodand a medium which are suitable when they are used to decode acompressed video signal.

BACKGROUND ART

In recent years, a video compressing technique represented by MPEG(Moving Picture Experts Group) 2 has been progressed and used in variousfields. In case of decoding video data encoded by MPEG2, the decoding isperformed every macroblock. When the video data which was decoded everymacroblock is stored in a frame memory, memory addresses of the videodata are sequentially allocated in a screen display order. That is, incase of a picture plane such that a Y macroblock constructed by 16×16pixels as shown in FIG. 1A consists of 720 480 pixels, the macroblocksare stored in the frame memory in a state where 45 macroblocks arearranged in the lateral direction and 30 macroblocks are arranged in thevertical direction as shown in FIG. 1B.

In case of allocating the memory addresses and storing the video data asmentioned above, such an allocation is a suitable address allocation incase of displaying the video data onto a screen on the basis of thevideo data stored in the frame memories. For example, in the framememory shown in FIG. 1A, when one line in the top portion of the screenis displayed, since the data in addresses 0000 to 0719 (the data as muchas 720 pixels) can be continuously read out, the occurrence of a pagemishit can be minimized. The “pagemis” denotes a time which is necessaryto precharge a sense amplifier provided in a memory such as a DRAM(Dynamic Random Access Memory) or the like (therefore, a process such asreading of the data or the like cannot be performed while precharging).

A DRAM is generally used as a frame memory. The DRAM is constructed byrows and columns and one row is constructed by charge accumulatingdevices comprising 256 (there is also a case of 512 or the like) 8columns. Among the charge accumulating devices, an 8-bit device hasexternal terminals of 8 pins and a 16-bit device has external terminalsof 16 pins. It indicates the number of bits which can be outputted byone clock. In case of the 8-bit device, 8 bits are outputted by oneclock. In case of the 16-bit device, 16 bits are outputted by one clock.Data can be continuously extracted in the same row. That is, in the8-bit device, since data of 256×8 bits has been accumulated in one row,data of 256 clocks (data of 256 bytes) can be continuously read out.

In a video decoder or the like, video data which is stored in a framememory is transmitted on a macroblock unit basis and a decoding order isalso set to a macroblock order. In one Y macroblock, one line isconstructed by 16 lines each consisting of 16 pixels (therefore, 16bytes). Therefore, for example, in case of the first Y macroblock, theaddresses are divided (instead of serial addresses) in a manner suchthat addresses 0000 to 0015 are allocated to the first line, addresses0720 to 0735 are allocated to the second line, and addresses 1440 to1455 are allocated to the third line, and the data is stored.

In case of decoding a stream of a digital video signal from a stream ofthe MPEG system, a process for detecting a sequence header(Sequence_Header) is first performed in an analyzing unit in a decodingapparatus. This is because unless the Sequence_Header is detected, apicture size and an aspect ratio cannot be specified.

That is, in the MPEG stream, there is a case where a picture plane ofthe SDTV (Standard Definition Television) or a picture plane of the HDTV(High Definition Television) is transmitted. For example, in a digitalsatellite broadcasting, there is a case where a program of a pictureplane of the SDTV and a program of a picture plane of the HDTV aremultiplexed and broadcasted in one channel. There is also a case where achannel of a program of a picture plane of the SDTV and channel of aprogram of a picture plane of the HDTV are switched.

In case of decoding the MPEG stream, first, it is necessary to set apicture size and an aspect ratio. In the MPEG system, a sequence layerhas been determined as a most significant layer. In one sequence, apicture size and a picture rate are identical. A Sequence_Header istransmitted at the head of each sequence. The picture size, aspectratio, picture rate, and the like have been described in the SequenceHeader. Therefore, hitherto, in case of decoding a bit stream of theMPEG system, first, in order to set the picture size and aspect ratio,the Sequence Header is detected. After the picture size and aspect ratiowere set from the

Sequence_Header, a decoding is started from the first picture which wasintrafield encoded or intraframe encoded.

After the data stored in one row was extracted, the process advances tothe next row and an apparatus has to wait for a time of about 6 clocksfor precharging until the data stored in the next row is read out. Inthis way, the precharge necessary to read out the data stored in anotherrow is called “pagemis” as mentioned above. In the foregoing 8-bitdevice, the pagemis occurs every 256 clocks (each time the data of 256bytes is extracted). In the foregoing 16-bit device, the pagemis occursevery 128 clocks. It will be understood that, as mentioned above, whenan amount of data which can be extracted by one clock increases, thenumber of times of occurrence (generating period) of the pagemisdecreases.

As shown in FIG. 1B, in the case where the video data is stored and thedata is sequentially read out one line by one and displayed in a mannersuch that the data in addresses 0000 to 0719 is read out to therebydisplay the first horizontal line and the data in addresses 0720 to 1439is subsequently read out to thereby display the second horizontal line,a pagemis occurs every 256 bytes in the 8-bit device. Since the pagemiscauses a loss time, the ability of a memory (DRAM) can be made the mostof by setting in such a manner that the pagemis does not occur aspossible.

In case of the foregoing video recorder, the video data is stored on amacroblock unit basis and read out on a macroblock unit basis. Since oneY macroblock is constructed by 16 lines as mentioned above, the pagemisoccurs each time one line is read out. That is, the pagemis occurs 16times whenever one Y macroblock is read out. In case of a chroma signal(Cb, Cr), since one macroblock is constructed by 8 lines each consistingof 8 bytes, the pagemis occurs 8 times whenever one Cb (Cr) macroblockis read out.

In case of using the 16-bit device for the frame memory, since the dataof 16 bits (2 bytes) can be outputted in response to one clock, thepagemis occurs at a rate of once per 8 clocks in the Y macroblock. Ineach of the Cb macroblock and the Cr macroblock, the pagemis occurs at arate of once per 4 clocks. Therefore, 8 clocks (one line of the Ymacroblock is constructed by 16 bytes) are necessary to read out oneline of the Y macroblock and 8 16 clocks (one Y macroblock isconstructed by 16 lines) are necessary to read out one Y macroblock.

On the other hand, assuming that a time of 6 clocks is expended for thepagemis of one time, it will be understood that the loss time that iscaused by the pagemis is equal to the time of 6 16 clocks because thepagemis occurs 16 times in case of reading out one Y macroblock. Thismeans that the ratio of the pagemis is fairly larger than the time (8 16clocks) which is necessary to read out one Y macroblock. In other words,it means that the loss time is large. Also in case of the macroblock ofchroma, the ratio of the loss time for the time that is necessary toread out the data is similarly large.

The pagemis also occurs in case of performing the decoding based on themotion compensation. That is, although the video data as much as onemacroblock is extracted from an arbitrary position in the frame memoryby a motion vector associated for the macroblock to be decoded, sincethe address is moved by an amount of one line each time one line of themacroblock is read out in a manner similar to the case mentioned above,the pagemis occurs. There is a problem such that if the user wants tomake the most of the ability of the DRAM or the like, it is necessary tosuppress the loss time such as a pagemis as small as possible.

The invention is made in consideration of such a circumstance and it isan object of the invention to suppress the occurrence of the pagemis byallocating addresses to video data of macroblocks in the ascending orderand storing the data.

In case of decoding the MPEG stream, first, the Sequence Header isdetected and the picture size and aspect ratio are set. However, if theMPEG stream is decoded after the Sequence_Header was detected, there isa problem such that it takes time to detect the Sequence Header and afairly long waiting time is necessary until the reproduction is started.

That is, the sequence layer of the MPEG system is a stream in which thepicture size and picture rate are identical. Although the SequenceHeader can be provided at a minimum GOP (Grop Of Picture) period, aperiod of the

Sequence_Header is not determined. Therefore, a maximum length ofsequence is equivalent to one video program. Thus, hitherto, forexample, when a channel of a satellite broadcasting is switched, thereis a case where it takes time to detect the Sequence Header and a fairlylong waiting time is necessary until the reproduction is started.

Another object of the invention is to provide video processing apparatusand method in which when Sequence Header information of an MPEG streamis not detected, information of the Sequence Header is predicted and adecoding is started, thereby enabling the MPEG stream to be immediatelydecoded.

DISCLOSURE OF THE INVENTION

According to the invention, there is provided a video processingapparatus comprising: input means for inputting video data of amacroblock unit; storage means for allocating addresses to the videodata inputted by the input means in an ascending order and storing thevideo data; and reading means for reading out the video data stored inthe storage means in the ascending order of the addresses.

According to the invention, there is provided a video processing methodcomprising: an inputting step of inputting video data of a macroblockunit; a storing step of allocating addresses to the video data inputtedby the inputting step in an ascending order and storing the video data;and a reading step of reading out the video data stored by the storingstep in the ascending order of the addresses.

According to the invention, there is provided a program of a medium,comprising: an inputting step of inputting video data of a macroblockunit; a storing step of allocating addresses to the video data inputtedby the inputting step in an ascending order and storing the video data;and a reading step of reading out the video data stored by the storingstep in the ascending order of the addresses.

In the video processing apparatus, video processing method, and mediumaccording to the invention, the addresses are allocated to the inputtedvideo data of the macroblock unit in the ascending order, the data isstored, and the stored video data is read out in the ascending order ofthe addresses.

According to the invention, there is provided a video processingapparatus for decoding a video stream having a layer structureconstructed by a sequence layer, a GOP layer, a picture layer, a slicelayer, a macroblock layer, and a block layer, comprising: SequenceHeader information predicting means for predicting Sequence Headerinformation on the basis of information which certainly appears in apicture; and decoding means for decoding video data by using theinformation predicted by the Header information predicting means whenthe Sequence Header is not detected.

The fourth byte of a Slice_Start_Code indicates a vertical position of aslice. Therefore, the number of pixels in the vertical direction of ascreen is obtained by detecting the fourth byte of the Slice_Start_Code.A (Macroblock_Address_Increment) indicates skip information of themacroblock. Therefore, the number of macroblocks in the horizontaldirection of the screen is obtained by accumulating the macroblockaddress increment each time the macroblock is decoded. By multiplying itby a size of macroblock, the number of pixels in the horizontaldirection of the screen is obtained.

If the MPEG stream is decoded by using the information predicted asmentioned above, the MPEG stream can be immediately decoded withoutdetecting the Sequence_Header.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A and 1B are diagrams for explaining a conventional method ofstoring video data;

FIG. 2 is a block diagram showing a construction of an embodiment of avideo processing apparatus to which the invention is applied;

FIG. 3 is a block diagram showing a detailed construction of a decodingunit 12 in FIG. 2;

FIG. 4 is a diagram for explaining a method of storing video dataaccording to the invention;

FIG. 5 is a diagram for explaining a method of storing the video dataaccording to the invention;

FIG. 6 is a diagram for explaining a reading of a predictive macroblock;

FIG. 7 is a block diagram of an example of an MPEG decoding apparatus towhich the invention is applied;

FIG. 8 is a schematic diagram for use in explanation of a layerstructure of the MPEG system;

FIG. 9 is a schematic diagram for use in explanation of slices;

FIG. 10 is a functional block diagram showing a construction of apredicting circuit of a picture size in the horizontal direction;

FIG. 11 is a schematic diagram for use in explanation of a macroblock;

FIG. 12 is a functional block diagram showing a construction of apredicting circuit of a picture size in the vertical direction;

FIG. 13 is a block diagram showing a construction of an embodiment of anaudio decoder 100;

FIG. 14 is a diagram for explaining an example of a message which istransmitted from a message transmitting program to a decoding program;

FIGS. 15A and 15B are diagrams for explaining a dummy block 131 and aBBB chain 132 in a memory 114;

FIG. 16 is a flowchart for explaining the processing operation of thedecoder 100; and

FIGS. 17A to 17C are diagrams for explaining media.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 2 is a block diagram showing a construction of a video processingapparatus for decoding data encoded by the MPEG2 system. Video datareceived by a tuner 1 is demodulation processed by a demodulationprocessing unit 2 and error correction processed by an error correctionprocessing unit 3. Further, the error correction processed video data issent to a software processing unit 4. The software processing unit 4 isconstructed by a software program which is executed by a CPU (CentralProcessing Unit) (not shown). A demultiplexer unit 11 in the softwareprocessing unit 4 demultiplexes the inputted data into the video dataand audio data every channel. The demultiplexed video data is decoded bya decoding unit 12 on the basis of the MPEG system.

In a display processing unit 13, an output of the decoding unit 12 isscanning line number converted, for example, from a high definitiontelevision signal represented by the HDTV to a television signal of theNTSC (National Television System Committee) system. A controller 14controls each unit of the software processing unit 4 besides thedecoding unit 12 and uses a cache memory 7 at an arbitrary time withrespect to processes of the video data. A DMAC (Direct Memory AccessController) 6 controls a DMA transfer from the cache memory 7 to a framememory 5. The frame memory 5 is constructed by, for example, a DRAM andthe stored video data is outputted to a video display apparatus (notshown).

FIG. 3 is a block diagram showing a more detailed construction of thedecoding unit 12 shown in FIG. 2. The video data outputted from thedemultiplexer unit 11 is inputted to a variable length decoding unit 31in the decoding unit 12. The variable length decoding unit 31 performs avariable length decoding process to the inputted video data, outputs aquantization step and the video data to an inverse quantizing unit 32,and outputs a motion vector to a motion compensation predicting unit 35,respectively. On the basis of the quantization step supplied from thevariable length encoding unit 31, the inverse quantizing unit 32inversely quantizes the video data which was variable length encodingprocessed. The inversely quantized video data is stored in the cachememory 7 through the controller 14.

In case of an intra-macroblock, the video data which was inverse DCTtransformation processed by an inverse DCT transforming unit 33 istransferred and stored as it is to the cache memory 7. In case of anonintra-macroblock, the motion compensation predicting unit 35arithmetically operates a predictive macroblock by using the motionvector supplied from the variable length decoding unit 31 and areference video image stored in the frame memory 5 and the video data isstored in the cache memory 7. An arithmetic operating unit 34 adds thevideo data (differential data) supplied from the inverse DCTtransforming unit 33 and the predictive macroblock supplied from thecache memory 7 to thereby obtain decoded video data and transfers it tothe cache memory 7. The video data stored in the cache memory 7 is DMAtransferred to the frame memory 5 on the basis of a control of the DMAC6.

The operation of the video decoding apparatus shown in FIG. 2 will nowbe described. The tuner 1 receives the video data and outputs it to thedemodulation processing unit 2. The demodulation processing unit 2 whichreceived the video data demodulation processes the inputted video dataand outputs it to the error correction processing unit 3. The errorcorrection processing unit 3 performs an error correcting process of thevideo data which was inputted and demodulation processed and outputs itto the software processing unit 4. In the software processing unit 4,the inputted video data is demultiplexed to the video data and audiodata every channel by the demultiplexer unit 11 and they are outputtedto the decoding unit 12.

The decoding unit 12 is controlled by the controller 14, decodes thevideo data by arbitrarily using the cache memory 7 and frame memory 5,and outputs the decoded video data to the display processing unit 13.The display processing unit 13 performs a scanning line numberconverting process to the decoded video data and stores it into theframe memory 5. The video data stored in the frame memory 5, namely, thevideo data subjected to the scanning line number converting process isoutputted to a video display apparatus (not shown) or the like.

The writing of the video data into the frame memory 5 in the decodingunit 12 shown in FIG. 3 will be described. The writing of the data intothe frame memory 5 and the reading of the data from the frame memory 5are performed on a macroblock unit basis. Since one Y macroblock isconstructed by 16×16 pixels, it is constructed by the data of 256 bytes.Each of the Cb macroblock and the Cr macroblock is constructed by 64 (=88) bytes. Therefore, as shown in FIG. 4, as for the Y macroblocks,continuous addresses are sequentially allocated in the ascending orderand those macroblocks are stored in a manner such that the Y macroblockwhich is read for the first time and located on the left top side on thescreen is stored in addresses 0000 to 0255 in the frame memory 5, the Ymacroblock which is subsequently read is stored in addresses 0256 to0511, and further, the Y macroblock which is subsequently read is storedin addresses 0512 to 0768.

Similarly, as shown in FIG. 5, as for the chroma macroblocks of the Cbmacroblocks and the Cr macroblocks, continuous addresses aresequentially allocated in the ascending order and those macroblocks arestored in a manner such that the chroma macroblock which is read for thefirst time is stored in addresses 0000 to 0063 and the chroma macroblockwhich is subsequently read is stored in addresses 0064 to 0128.

By storing the video data of the macroblock unit as mentioned above, thepagemis never occurs in both of the Y macroblock and the Cb (Cr)macroblock at the time of reading out one macroblock. That is, thepagemis occurs when the row as a target to be read out is switched, andone row is constructed by 256 bytes (hereinafter, properly, 256 bytesare called one page and a delimiter of each unit is called a pagedelimiter). Therefore, the pagemis occurs at least every readingoperation of 256 bytes. However, if the data is stored in the framememory 5 as mentioned above, the page delimiter is generated everymacroblock with respect to the Y macroblock. The page delimiter isgenerated every 4 macroblocks with respect to the Cb (Cr) macroblock.

Since it is sufficient to reduce the number of times of switching of therow in order to minimize the pagemis (loss time), the loss time can bereduced by storing the data into the frame memory 5 as mentioned above.

Explanation will now be made with respect to the case of extracting thepredictive video data by the motion compensation vector from the framememory 5 in which the video data has been stored. The case where the Ymacroblock is set to a target will be described as an example. Asmentioned above, one Y macroblock is constructed by 16 16 pixels (16 16bytes).

FIG. 6 is a diagram showing a positional relation of a macroblock MA n(macroblock which is decoded) to be predicted from a macroblock MA m bypredicting a picture plane which is displayed on a screen of the screendisplay apparatus. Among motion compensation vectors of MA n, the motioncompensation vector in the lateral (horizontal) direction in the diagramis expressed by a vector x and the motion compensation vector in thelongitudinal (vertical) direction in the diagram is expressed by avector y. The vectors x and y are used for deciding address offsets inthe horizontal and vertical directions by which the data should beextracted from the upper left edge portion of the macroblock MA_m.

A case where the macroblock MA m whose position is unconditionallydetermined by the vectors x and y overlaps with up to four macroblocksas shown in FIG. 6 is predicted. If those four macroblocks are describedby a macroblock MA 0, a macroblock MA 1, a macroblock MA 2, and amacroblock MA 3 in order from the upper left to the lower right,relations between the macroblock MA n to be decoded and the vectors xand y are as shown by the following equations.MA_(—)0=MA_n+x/16+MA_w×y/16MA_(—)1=MA_(—)0+1

MA_(—)2=MA_(—)0+MA_wMA_(—)3=MA_(—)0+MA_w+1  (1)

where, x and y denote magnitudes of the vectors x and y and MA windicates the number of macroblocks arranged on a line in the horizontaldirection of the screen.

Further, the addresses (head addresses) at the upper left edges in theportions of the macroblocks MA 0, MA 1, MA 2, and MA 3 which overlapwith the macroblock MA m are calculated by the following equations. Thehead addresses of the macroblocks MA_0, MA_1, MA_2, and MA_3 are assumedto be addresses ad_0, ad_1, ad_2, and ad_3, respectively.ad_(—)0=ad_MA 0+x%16+16x(y%16)ad_(—)1=ad_MA 1+16x(y%16)ad_(—)2=ad_MA 2+x%16ad_(—)3=ad_MA 3  (2)

where, ad MA 0, ad MA 1, ad MA 2, and ad MA 3 denote head addresses ofthe macroblocks MA 0, MA 1, MA 2, and MA 3, x%16 denotes a remainderobtained when the magnitude of the vector x is divided by 16, andsimilarly, y%16 denotes a remainder obtained when the magnitude of thevector y is divided by 16.

The number of horizontal data and the number of vertical lines in theportions of the macroblocks MA_0, MA_1, MA_2, and MA_3 which overlapwith the macroblock MA m are calculated by the following equations. Inthe following equations, MA_0_h denotes the number of horizontal data inthe overlapped portion of the macroblock MA_m and the macroblock MA_0and MA_0 v denotes the number of vertical lines in the overlappedportion of the macroblock MA_m and the macroblock MA_0. The otherdescriptions also indicate similar meanings.MA_(—)0_h=16−(x%16), MA_(—)0_v=16−(y%16)MA_(—)1_h=16−MA_(—)0_h, MA_(—)1_v=MA_(—)0_vMA_(—)2_h=MA_(—)0_h, MA_(—)2_v=16−MA_(—)0_vMA_(—)3_h=MA_(—)1_h, MA_(—)3_v=MA_(—)2_v  (3)

As mentioned above, in case of extracting the data from the fourmacroblocks MA_0, MA_1, MA_2, and MA_3, the pagemis occurs four times.In case of extracting the data from the same macroblock (onemacroblock), no pagemis occurs. That is, there is a possibility suchthat the pagemis occurs at least 0 time and at most four times.

However, two banks are provided in the DRAM or the like and the writingor reading of the data is performed by switching the banks. In themacroblock, the data is alternately written in the different banks everyhorizontal line. Therefore, in case of performing the writing by usingtwo banks 0 and 1 as shown in FIG. 6, the following processes arerepeated: namely, the data of one horizontal line of the macroblock MA 0is read out from the bank 0; the data of one horizontal line of themacroblock MA 2 is read out from the bank 1; the data of one horizontalline of the macroblock MA 1 is read out from the bank 0; andsubsequently, the data of one horizontal line of the macroblock MA 3 isread out from the bank 1.

If the data is read out by switching the banks 0 and 1 as mentionedabove, the pagemis does not occur. That is, since each of the banks 0and 1 has an independent sense amplifier, it can be independently set toan active state (precharging state). Therefore, even if the macroblocksstored in the other bank are continuously read out (even if the data isread out by switching the banks), the pagemis (loss time) due to theswitching can be ignored. Thus, only the pagemis which occurs when thedata of the macroblock MA_0 is first read out becomes the loss time.

Although the case of reading out the Y macroblock has been describedabove in the equations (1) to (3), in case of the chroma (Cb, Cr)macroblocks, it is sufficient to calculate by replacing 16 with 8 ineach equation.

By writing and reading the video data as mentioned above, a time whichis required for data transfer in the time necessary for reading out oneY macroblock is equal to 8 16 clocks. Assuming that the time of onepagemis is equal to 6 clocks, the loss time due to the pagemis is equalto 6 1 clocks, so that the ratio of the loss time due to the pagemis tothe time for data transfer can be reduced. Similarly, even in case ofreading out one Cb (Cr) macroblock, the ratio of the loss time due tothe pagemis to the time for data transfer can be reduced.

Processes in case of outputting the video data to the video displayapparatus (not shown) will now be described. In the case where the videodata of the macroblock unit was stored in a manner such that a dataarrangement on the screen and a data arrangement in the frame memory arethe same as shown in FIG. 1B, the video display is performed by readingout the data in the ascending order of the addresses. However, in caseof storing the macroblocks by one or two lines as shown in FIG. 4 (FIG.5), a video image cannot be displayed by reading out the data in theascending order of the addresses.

In other words, in the case where the video data was stored as shown inFIG. 1B, the video data of 16 pixels (16 bytes) is read out from eachmacroblock in order to display one line on the screen. Even in the casewhere the video data was stored as shown in FIG. 4 (FIG. 5), the videodata of every 16 bytes has to be similarly read out from eachmacroblock. By this method, the row has to be switched each time 16bytes are read out and the pagemis occurs each time. To eliminate suchan inconvenience, it is sufficient to perform an address conversion andoutput the video data to the video display apparatus as shown below.

The cache memory 7 shown in FIG. 3 is used as a temporary buffer and thevideo data of one slice is loaded into the cache memory 7 from the framememory 5 and converted into a memory structure (address) as shown inFIG. 1B. In case of using an SRAM (Static RAM) as a cache memory 7,since no page exists like a DRAM, no pagemis occurs.

A case of converting the addresses from the state where the Ymacroblocks have been stored as shown in FIG. 4 to a state where the Ymacroblocks have been stored as shown in FIG. 1B will be specificallydescribed. The video data in addresses 0000 to 0015 is read out as videodata of the first line from the frame memory 7 in which the video datahas been stored as shown in FIG. 4 and is stored in addresses 0000 to0015 in the cache memory 7. Then, the video data in addresses 0016 to0031 is read out as video data of the second line and stored inaddresses 0720 to 0735 in the cache memory 7. Subsequently, the videodata in addresses 0032 to 0047 is read out as video data of the thirdline and stored in addresses 1440 to 1455 in the cache memory 7. Suchprocesses are repeated.

In case of reading out the video data from the frame memory 7 asmentioned above, since the reading operation itself is executed in theascending order of the addresses, the pagemis occurs only every 256bytes. The video data stored in the cache memory 7 is transferred againto the frame memory 5 and stored. The video data stored in the framememory 5 as shown in FIG. 1B is outputted to the video display apparatus(not shown).

Since the re-transfer from the cache memory 7 to the frame memory 5 isperformed in the address order of the one-to-one correspondingrelationship, if the cache memory 7 is constructed by the SRAM, nopagemis occurs, so that the loss time due to the above processes doesnot occur.

Although the video data is transferred again from the cache memory 7 tothe frame memory 5 in the above description, it can be also transferredfrom the cache memory 7 to a frame memory (DRAM) for displaying orscaling which is different from the frame memory 5.

By writing and reading the video data of the macroblocks as mentionedabove, the macroblocks obtained after completion of the decoding can besequentially stored in the same page in the frame memory comprising theDRAM or the like. Therefore, the number of times of occurrence of thepagemis can be reduced by using a burst transfer function of the DRAMand a memory band width can be improved. Since the macroblocks have beenstored in the same page in the frame memory, even in case of extractinga reference macroblock by the motion compensation vector, the number oftimes of occurrence of the pagemis can be reduced by using a bursttransfer of the DRAM and a memory band width can be improved.

When the macroblocks are stored in the frame memory, by alternatelystoring them into the other bank in the DRAM every horizontal width ofthe screen, even in case of extracting the predictive data from aplurality of (up to four) macroblocks, the pagemis can be minimized.Further, since the memory can be constructed by two banks, a structureof the memory system can be simplified and also realized by a DRAM of asmall (less) capacity, so that flexibility is high.

A video processing apparatus in which when the Sequence_Headerinformation of the MPEG stream is not detected, the information ofSequence_Header is predicted and the decoding is started, therebyenabling the MPEG stream to be immediately decoded will now bedescribed. FIG. 7 shows an example of the video processing apparatus towhich the invention is applied. In FIG. 7, the MPEG stream from thedemultiplexer 11 is supplied to the MPEG decoder 12 and supplied to aSequence Header predicting circuit 16. The MPEG decoder 12 executes adecoding process of the MPEG stream.

The MPEG stream is decoded by the MPEG decoder 12 and a stream of thedigital video data is outputted from the MPEG decoder 12. An output ofthe MPEG decoder 12 is supplied to a display 15 through the displayprocessing unit 13. Thus, a picture plane based on the MPEG stream isdisplayed on the display 15.

In the case where the MPEG stream is decoded by the MPEG decoder 12,first, it is necessary to set a picture size, an aspect ratio, or thelike. Those information can be detected by the Sequence_Header. However,there is a case where it takes time to detect the Sequence Header.

Therefore, the Sequence Header predicting circuit 16 is provided. TheSequence Header predicting circuit 16 predicts the information to betransmitted by the Sequence Header by using the information which iscertainly included in each picture.

That is, in the Sequence Header, the information such as picture size,aspect ratio, frame rate, VBV buffer size, quantization matrix, and thelike is sent. The Sequence Header predicting circuit 16 predicts thepicture size in the vertical direction by using the information ofslices. The picture size in the horizontal direction is predicted byusing the information of the macroblock. The aspect ratio is predictedby using the picture size in the vertical direction and the picture sizein the horizontal direction which were predicted. By detecting adecoding timing by a time stamp of DTS/PTS or the like, the frame rateis predicted. An output of the Sequence Header predicting circuit 16 issupplied to the MPEG decoder 12 and supplied to the display processingunit 13.

In case of decoding the MPEG stream by the MPEG decoder 12, if theSequence Header can be detected, the picture size, aspect ratio, framerate, VBV buffer size, quantization matrix, progressive sequence, andthe like are set by using the information of the Sequence_Header.

When the Sequence_Header cannot be detected by the MPEG decoder 12, thepicture size, aspect ratio, frame rate, VBV buffer size, quantizationmatrix, progressive sequence, and the like which were predicted by theSequence_Header predicting circuit 16 are set.

When the Sequence_Header cannot be detected by the MPEG decoder 12, thepicture size and aspect ratio which were predicted by theSequence_Header predicting circuit 16 are transmitted to the displayprocessing circuit 13. A display screen is set in accordance with thepicture size and aspect ratio which were predicted by theSequence_Header predicting circuit 16.

In the MPEG decoding apparatus to which the invention is applied asmentioned above, the Sequence_Header predicting circuit 16 forpredicting the information of the Sequence_Header is provided. When theSequence_Header cannot be detected, a decoding process is performed byusing the picture size and aspect ratio predicted by the Sequence_Headerpredicting circuit 16. Therefore, for example, even when the channelsare switched in the satellite broadcasting, there is hardly a waitingtime and the reproduction can be started.

A principle and a construction of the Sequence_Header predicting circuit16 will now be specifically explained.

As shown in FIG. 8, a data structure of the MPEG is a layer structure ofa sequence layer, a GOP layer, a picture layer, a slice layer, amacroblock layer, and a block layer.

The sequence layer is a group of picture planes having a series of sameattributes, for example, the same picture size and the same video rate.The GOP layer is a group of picture planes serving as a unit of a randomaccess. The picture layer is a group of attributes which are common toone picture plane. The slice layer is a group obtained by finelydividing one picture plane. The macroblock layer is a group obtained byfurther finely dividing the slice layer and is a group for performing amotion vector detection or the like. The block layer is a block itselffor performing a DCT transformation.

A Sequence_Header (SH) is provided at the head of the sequence. In theSequence_Header, the following items are described.

Horizontal_Size_Value: the number of pixels in

the horizontal direction of the video image

Vertical_Size_Value: the number of pixels in

the vertical direction of the video image

Aapect_Ratio_Information: aspect ratio

Frame_Rate_Code: display period of the video

image

VBV_Buffer_Size: capacity of a virtual buffer

for controlling a generation code amount (VBV)

Load Quantization_Matrix: quantization matrix

for macroblocks

Progressive_Sequence: showing a progressive scan

And the like.

Among them, the information of the number of pixels in the verticaldirection of the video image (Vertical_Size_Value) can be predicted fromthe information of slices.

That is, FIG. 9 shows a construction of slices in one picture. As shownin FIG. 9, one picture is divided into a plurality of slices. The sliceat the leftmost edge of the top stage (Bs=1) in one picture is set toSlice (1, 0). The second slice from the left of the top stage is set toSlice (1, 1). In a manner similar to the above, the slice at theleftmost edge of the bottom stage (Bs=N) in one picture is set to Slice(N, 0) . The second slice from the left of the bottom stage is set toSlice (N, 1).

Although a plurality of slices can exist in the horizontal direction asmentioned above, the slice is certainly switched to the slice which hasa new slice ID as a start code at the left edge of the picture.Therefore, a size in the vertical direction of one picture can bepredicted by using the slice.

That is, a Slice_Start_Code as a sync code indicative of the start ofthe slice layer is inserted at the head of each slice. TheSlice_Start_Code is shown by “00 00 01 01 AF” of a hexadecimal number.Last one byte (“01 AF” of the fourth byte) of the code indicates thevertical position of the slice by the hexadecimal number. As mentionedabove, the 4th byte of the Slice_Start_Code corresponds to the positionin the vertical direction of the slice and this means the same number inthe same line.

From the above explanation, the number of pixels in the verticaldirection of the screen can be predicted by detecting the 4th byte ofthe Slice_Start_Code at the bottom stage in one picture.

FIG. 10 is a functional block diagram showing a construction forpredicting the number of pixels in the vertical direction of the screenfrom the information of the slice as mentioned above. In FIG. 10, theMPEG stream is supplied to an input terminal 41. A Picture Start Code inthe MPEG stream is detected by a Picture Start Code detecting unit 42. ASlice Start Code is detected by a Slice Start Code detecting unit 43.

The Picture Start Code is a code showing the start of the picture layer.The Slice_Start_Code is a code showing the start of the slice layer. The4th byte of the Slice Start Code indicates the vertical position.

An output of the Slice_Start_Code detecting unit 43 is sent to a 4thbyte extracting unit 44. In the 4th byte extracting unit 44, theinformation of the 4th byte of the Slice_Start_Code is extracted. Anoutput of the 4th byte extracting unit 44 is sent to a vertical sizeregister 45.

The head of one picture can be detected by detecting the Picture StartCode by the Picture Start Code detecting unit 42. When the head of onepicture is detected, the vertical size register 45 is reset.

Whether the Slice_Start_Code has been detected by the Slice_Start_Codedetecting unit 43 or not is discriminated.

In the case where the Slice_Start_Code is detected by theSlice_Start_Code detecting unit 43, the information of the 4th byte ofthe Slice Start Code is extracted by the 4th byte extracting unit 44 andthe information of the 4th byte of the Slice Start Code is supplied tothe register 45. Until the next Picture Start Code is detected by thePicture Start Code

detecting unit 42, when the Slice Start Code is detected by the SliceStart Code detecting unit 43, the information of the 4th byte of theSlice Start Code is extracted by the 4th byte extracting unit 44 and theregister 45 is updated on the basis of this value.

When the next Picture Start Code is detected by the Picture Start Codedetecting unit 42, the information in the register 45 is inputted asinformation of the number of pixels in the vertical direction into avertical size register 46.

The Slice Start Code is detected from the head to the end of the pictureby the Slice Start Code detecting unit 43 in this manner, and when theSlice Start Code is detected, the value of the 4th byte is extracted bythe 4th byte extracting unit 44 and inputted to the vertical sizeregister 45, so that a predictive value of the number of pixels in the

vertical direction is derived from the value in the vertical sizeregister 46.

The number of pixels in the horizontal direction of the video image(Horizontal Size Value) can be predicted from the information of themacroblocks. That is, as shown in FIG. 11, the macroblocks are obtainedby further dividing the slice.

In this example, there are macroblocks MB1, MB2, and

MB3 in a Slice (1, 0) and there are macroblocks MB4, MB5, MB6, and MB7in a Slice (1, 1). The skipped macroblocks exist between the macroblocksMB2 and MB3 of the Slice (1, 0).

A Macroblock Address Increment is provided at the head of the macroblockand it is a VLC (variable length code) indicative of the macroblocks tobe skipped. Although the Macroblock Address Increment is equal to “1” inthe ordinary adjacent macroblocks, when the macroblocks to be skippedexist, it is set to a value increased by the number of skippedmacroblocks.

The value of the Macroblock Address Increment in one slice, therefore,is accumulated every macroblock, and in the case where a plurality ofslices exist in the horizontal direction, by adding the accumulatedvalues of the Macroblock Address Increment in each slice, the number ofmacroblocks in the lateral direction per picture plane can berecognized. By

multiplying the recognized number by the size of macroblock, namely,“16” with respect to the luminance signal or “8” with regard to the twocolor difference signals, the number of pixels in the horizontaldirection per picture can be predicted.

FIG. 12 is a functional block diagram showing a construction forpredicting the number of pixels in the horizontal direction of thepicture plane from the information of the macroblock as mentioned above.

In FIG. 12, the MPEG stream is supplied to an input terminal 51. TheSlice Start Code in the MPEG stream is detected by a Slice Start Codedetecting unit 52 and the Macroblock Address Increment is detected by aMacroblock Address Increment detecting unit 53.

In case of predicting the number of pixels in the horizontal direction,irrespective of the first Picture Coding Type, the decoding is performedin the MPEG decoder 12 by an intra-process only in such a picture. Whenthe decoding of the macroblock is performed, a signal indicating thatthe decoding of the macroblock has been performed is outputted. Thesignal indicating that the decoding of the macroblock has been performedis supplied from an input terminal 62 to a decoding macroblock detectingunit 57.

In the case where the slice at the leftmost edge of one line is detectedby the Slice Code detecting unit 52, register 55, registers 58A, 58B, .. . , and a horizontal size register 61 are cleared. In the MacroblockAddress Increment detecting unit 53, the Macroblock Address Increment isdetected.

The Macroblock Address Increment indicates skip information of themacroblocks and increment values corresponding to “1” to “33” arewritten by variable length codes. When the Macroblock Address Incrementis equal to or larger than “33”, a Macroblock Escape is also referredto.

An output of the Macroblock Address Increment detecting unit 53 issupplied to a VLC decoding unit 54. The value of the Macroblock AddressIncrement is decoded in the VLC decoding unit 54.

An output of the VLC decoding unit 54 is supplied to an adder 56. Anoutput of the register 55 is supplied to the adder 56. An output of thedecoding macroblock detecting unit 57 is supplied to the register 55.When the fact that the decoding of the macroblocks has been performed isdetected from the output of the decoding macroblock detecting unit 57,

the value of the present Macroblock Address Increment and that of theprevious Macroblock Address Increment are added in the adder 56 and thevalues of the Macroblock Address Increment are accumulated. Theaccumulated value of the Macroblock Address Increment in each slice ofthe same horizontal line is consequently obtained.

The output of the register 55 is supplied to the registers 58A, 58B, . .. . In the case where there are a plurality of slices in the horizontaldirection, the registers 58A, 58B, . . . fetch the accumulated value ofthe Macroblock Address Increment in each slice. An output of the SliceStart Code detecting unit 52 is supplied to the registers 58A, 58B, . .. . The accumulated value of the Macroblock Address Increment isinputted every slice into the registers 58A, 58B,

. . . in response to the output of the Slice Start Code detecting unit52. For example, the accumulated value of the Macroblock AddressIncrement in the first slice of the same horizontal line is inputted tothe register 58A. The accumulated value of the Macroblock AddressIncrement in the next slice of the same horizontal line is inputted tothe register 58B.

Outputs of the registers 58A, 58B, . . . are supplied to an adder 59. Inthe adder 59, the accumulated value of the Macroblock Address Incrementin each slice is added. As mentioned above, by adding the value of theMacroblock Address Increment accumulated in each slice, the number ofmacroblocks in the lateral direction per picture plane can be obtained.

An output of the adder 59 is supplied to a multiplier 60. The multiplier50 multiplies the number of macroblocks by the size of macrblock,thereby calculating the number of pixels in the horizontal direction.That is, in the multiplier 60, by multiplying the number of macroblocksby the size in the horizontal direction of macrblock, the number ofpixels in the horizontal direction per picture is calculated. The numberof pixels in the horizontal direction obtained in this manner issupplied to the horizontal size register 61.

As mentioned above, in the adder 56 and register 55, the value of theMacroblock Address Increment in one slice is accumulated everymacroblock, and the value of the Macroblock Address Incrementaccumulated in each slice is added by the adder 59, so that the numberof macroblocks in the lateral direction per picture plane is calculated.In the multiplier 60, it is multiplied by the size of macroblock, sothat the number of pixels in the horizontal direction per picture isobtained.

The aspect ratio (Aapect_Ratio_Information) can be predicted on thebasis of the number of pixels in the horizontal direction and the numberof pixels in the vertical direction of the video image which wereobtained as mentioned above. If the picture size is equal to (720×480),the TV type is the SDTV. Therefore, it is predicted that the aspectratio is equal to (4:3). If the picture size is equal to (920×1080), theTV type is the HDTV. Therefore, it is predicted that the aspect ratio isequal to (16:9).

A display period (Frame_Rate_Code) of the video image is indirectlypredicted by recognizing the decoding timing by the time stamp of theDTS/PTS or the like.

As for the size (VBV Buffer Size) of the virtual buffer (VBV) forcontrolling the generation code amount, the buffer having the maximumsize in the possible level profile is prepared. Similarly, also withrespect to the decoding video image, the capacity of the ordinarypossible maximum size in the relevant level profile is assured.

A quantization matrix for macroblocks (Load_Quantization Matrix) issubstituted by a default value.

A Progressive_Sequence is substituted by Progressive_Frame in thePicture_Coding_Type which is multiplexed every frame.

Although the case of decoding the stream of the MPEG1 or MPEG2 systemhas been described in the above example, the invention can be alsosimilarly applied to the case of decoding a stream of a similar layerstructure.

The decoding of the MPEG video stream by the software has been describedabove. A decoding of an MPEG audio stream by software will now bedescribed hereinbelow. In an MPEG audio decoder, MPEG audio data whichis supplied from the outside is decoded by a decoding module, thedecoded data is supplied to a codec module, it is digital/analogconverted by the codec module, and the converted analog data isoutputted to an external apparatus.

However, when the MPEG audio data decoded by the decoding module isoutputted to the codec module, if a channel of the MPEG audio data isswitched, the data before the switching of the channels is outputted fora predetermined time, so that it is inconvenient.

Therefore, in the audio decoder by the software in the invention, mutingdata is outputted from the decoding module to the codec module at thetime of channel switching.

FIG. 13 is a block diagram showing a construction of an embodiment of anaudio decoder 100.

The user inputs desired information by operating an input unit 111. Forexample, by operating the input unit 111, the user turns “ON” a powersource of the decoder 100, switches the channels of MPEG audio datawhich is supplied from the outside, or instructs the muting.

A CPU 112 reads out programs stored in memories 115 to 117, which willbe explained hereinlater, and executes the programs on the basis of theinformation supplied from the input unit 111. A data change-over switch113 switches the MPEG audio data and program data. The MPEG audio datawhich is supplied from the outside is inputted to a memory 114 through aDMA (Direct Memory Access) bus 120 and the data change-over switch 113and stored.

An AC link program linked with the power source has been stored in thememory 115. When the user turns “ON” the power source of the decoder 100through the input unit 111, the CPU 112 reads out the AC link programthrough the data change-over switch 113 and executes it.

A message transmitting program which corresponds to the informationinputted from the input unit 111 and is used for transmitting a messagehas been stored in the memory 116. This message is transmitted to adecoding program and a data transfer processing program stored in thememory 117, which will be explained hereinlater. That is, when the userinputs desired information through the input unit 111, the CPU 112 readsout the message transmitting program through the data change-over switch113, executes it, and transmits the message corresponding to theinputted information to the decoding program and the data transferprocessing program.

The decoding program for decoding the MPEG audio data stored in thememory 114 at a timing of the supplied message and the data transferprocessing program have been stored in the memory 117. The CPU 112decodes the MPEG audio data stored in the memory 114 at the timing ofthe message which is supplied and allows the data obtained aftercompletion of the decoding to be stored again in the memory 114.

Subsequently, the CPU 112 reads out and executes the data transferprocessing program and transfers the MPEG audio data obtained aftercompletion of the decoding and stored in the memory 114 to an outputbuffer 118.

At the time of the power source “ON”, the channel switching, and themuting instruction, dummy data (data of “0”) which has previously beenstored in the memory 114 is transferred to the output buffer 118.

The data temporarily stored in the output buffer 118 is supplied to acodec 119 through the DMA bus 120. The codec 119 digital/analog convertsthe supplied MPEG audio data obtained after completion of the decodingand outputs the converted data to an external apparatus (not shown)through the DMA bus 120.

Subsequently, an example of the message which is transmitted from themessage transmitting program in response to the decoding program and thedata transfer processing program will now be described with reference toFIG. 14.

First, when the power source is turned “ON” (at time tl) by the userthrough the input unit 111, a “U” message is transmitted to the decodingprogram and the data transfer processing program. The “U” message isused for showing that the power source has been turned on. A “W” messageis subsequently transmitted to the decoding program and the datatransfer processing program for a predetermined time (T2). The “W”message shows “wait for decoding” and T2 denotes the time which isrequired until the MPEG audio data of a predetermined amount is storedin the memory 14.

When the MPEG audio data of the predetermined amount is stored in thememory 114, an “F” message is transmitted to the decoding program andthe data transfer processing program. The “F” message indicates “startthe decoding”. When this message is received, the CPU 112 starts thedecoding of the MPEG audio data stored in the memory 114. After that, an“N” message is transmitted to the decoding program and the data transferprocessing program (T3). The “N” message indicates “continue thedecoding”. The CPU 112 continues the decoding in accordance with thismessage.

When the user operates the input unit 111 and switches the channel, the“W” message is transmitted to the decoding program and the data transferprocessing program for a predetermined time (T5). The CPU 112 waitsuntil the new MPEG audio data is decoded. T5 denotes the time which isrequired until the MPEG audio data of a predetermined amount obtainedafter completion of the channel switching is stored in the memory 114.

When the MPEG audio data of the predetermined amount is stored in thememory 114, the “F” message is transmitted to the decoding program andthe data transfer processing program. The CPU 112 starts the decoding ofthe MPEG audio data. After that, the “N” message is transmitted to thedecoding program and the data transfer processing program (T6). The CPU112 continues the decoding.

When the user operates the input unit 111 and turns “OFF” the decoder100 (time t7), a “D” message is transmitted to the decoding program andthe data transfer processing program. The decoding of the MPEG audiodata is finished.

Subsequently, a function such that the CPU 112 switches the data whichis transferred from the memory 114 to the output buffer 118 on the basisof the message will be described with reference to FIG. 15.

FIG. 15A shows a dummy block 131 which has previously existed in thememory 114. “0” data has been stored in the dummy block 131. FIG. 15Bshows a BBB chain 132 in which the MPEG audio data obtained aftercompletion of the decoding is stored. The BBB chain 132 is constructedby six blocks of an (a) block 141 to an (f) block 146 and stores theMPEG audio data obtained after completion of the decoding in order fromthe (a) block 141.

In the case where the “W” message is transmitted (for example, time T2and time T5 in FIG. 14) from the message transmitting program inresponse to the data transfer processing program, the CPU 112 reads outthe “0” data from the dummy block 131 in the memory 114 and transfersthe read-out “0” data to the output buffer 118. Thus, at the time ofturn “ON” of the power source and the channel switching, the muting datais outputted to the codec 119 for a predetermined time.

When the “F” message or “N” message is transmitted (for example, time T3and time T6 in FIG. 14) from the message transmitting program inresponse to the data transfer processing program, the CPU 112 reads outthe data obtained after completion of the decoding in order from the (a)block 141 of the BBB chain 132 in the memory 114 and transfers theread-out data to the output buffer 118. Thus, the data after thedecoding is outputted to the codec 119 while the MPEG audio data isbeing decoded.

Subsequently, the processing operation in the case where when the powersource of the decoder 100 is turned on, the CPU 112 switches the data tobe transferred from the memory 114 to the output buffer 118 on the basisof the message will be described with reference to a flowchart of FIG.16.

First, in step S11, when the user operates the input unit 111 and turns“ON” the power source of the decoder 100, the CPU 112 reads out the AClink program from the memory 115 and executes it.

Subsequently, in step S12, the CPU 112 reads out the messagetransmitting program from the memory 116 and executes it. At this time,the “U” message indicative of the turn “ON” of the power source istransmitted to the decoding program and the data transfer processingprogram.

In step S13, the “W” message indicative of the waiting for the start ofthe decoding is transmitted to the decoding program and the datatransfer processing program.

In step S14, the CPU 112 reads out the “0” data from the dummy block 131in the memory 114 and transfers the data to the output buffer 118.

In step S15, the CPU 112 discriminates whether the MPEG audio data ofthe predetermined amount has been stored in the memory 114 or not. Instep S15, if it is determined that the MPEG audio data of thepredetermined amount is not stored in the memory 114, the processingroutine is returned to step S13. The subsequent processes arerepetitively executed.

In step S15, if it is determined that the MPEG audio data of thepredetermined amount has been stored in the memory 114, the processingroutine advances to step S16. The “F” message indicative of the start ofthe decoding is transmitted to the decoding program and the datatransfer processing program.

In step S17, the CPU 112 starts the decoding of the MPEG audio datastored in the memory 114 and stores the decoded data into the BBB chain132 in the memory 114.

In step S18, the CPU 112 reads out the decoded data from the BBB chain132 in the memory 114 and transfers the data to the output buffer 118.

In step S19, the CPU 112 discriminates whether all of the MPEG audiodata has been decoded or not. In step S19, if it is decided that all ofthe MPEG audio data is not decoded, the processing routine is returnedto step S16 and the subsequent processes are repetitively executed. Instep S19, if it is decided that all of the MPEG audio data has beendecoded, the processing operation is finished.

A medium which is used for installing a program to execute the foregoingseries of processes into a computer and setting a state where they canbe executed by the computer will now be described with reference to FIG.17.

As shown in FIG. 17A, the program can be provided to the user in a statewhere it has previously been installed in a hard disk 152 or asemiconductor memory 153 as a recording medium built in a personalcomputer 151 (corresponding to a video decoding apparatus).

Otherwise, as shown in FIG. 17B, the program can be provided as packagesoftware in a state where it is temporarily or permanently stored in arecording medium such as floppy disk 161, CD-ROM 162, MO disk 163, DVD164, magnetic disk 165, semiconductor memory 166, or the like.

Further, as shown in FIG. 17C, the program can be also provided in amanner such that it is transferred from a download site 171 to apersonal computer 173 through a satellite 172 in a wireless manner ortransferred to the personal computer 173 through a network 181 such aslocal area network or Internet in a wired or wireless manner and isdownloaded to a built-in hard disk or the like in the personal computer173.

The “medium” in the specification denotes a broad concept including allof those media.

In the video processing apparatus, video processing method, and mediumaccording to the invention, the addresses are allocated to the inputtedvideo data of the macroblock unit in the ascending order, the video datais stored, and the stored video data is read out in the ascending orderof the addresses. Therefore, the number of times of occurrence of thepagemis can be suppressed.

According to the video processing apparatus and method of the invention,when the Sequence_Header is not detected, the 4th byte of the SliceStart code is detected, the number of pixels in the vertical directionof the picture plane is predicted, the value of theMacroblock_Address_Increment is accumulated, the number of macroblocksin the horizontal direction of the picture plane is obtained, it ismultiplied by the size of macroblock, and the number of pixels in thehorizontal direction of the picture plane is predicted. The decoding ofMPEG is performed by using the information predicted as mentioned above.Thus, the MPEG stream can be immediately decoded even if theSequence_Header is not detected.

INDUSTRIAL APPLICABILITY

The invention is suitable for use in decoding of the video signalcompressed by MPEG.

1. A video processing apparatus for decoding a video stream having a layer structure constructed by a sequence layer, a GOP layer, a picture layer, a slice layer, a macroblock layer, and a block layer, comprising: Sequence_Header information predicting means for predicting Sequence_Header information on the basis of information which certainly appears in a picture; and decoding means for decoding video data by using the information predicted by said Header information predicting means when said Sequence_Header is not detected.
 2. A video processing apparatus according to claim 1, wherein said Sequence_Header information predicting means includes vertical pixel number predicting means for predicting the number of pixels in the vertical direction of a picture plane from information in a slice.
 3. A video processing apparatus according to claim 1, wherein said Sequence_Header information predicting means includes horizontal pixel number predicting means for predicting the number of pixels in the horizontal direction of a picture plane from information in a macroblock.
 4. A video processing apparatus according to claim 1, wherein said Sequence_Header information predicting means includes aspect ratio predicting means for predicting the number of pixels in the vertical direction of a picture plane from information in a slice, predicting the number of pixels in the horizontal direction of the picture plane from information in a macroblock, and predicting an aspect ratio of the picture plane from said predicted number of pixels in the vertical direction and said predicted number of pixels in the horizontal direction.
 5. A video processing method of decoding a video stream having a layer structure constructed by a sequence layer, a GOP layer, a picture layer, a slice layer, a macroblock layer, and a block layer, comprising the steps of: predicting Sequence Header information on the basis of information which certainly appears in a picture; and decoding video data by using said predicted information when said Sequence_Header is not detected.
 6. A video processing method according to claim 5, wherein when said Sequence_Header information is predicted, the number of pixels in the vertical direction of a picture plane is predicted from information in a slice.
 7. A video processing method according to claim 5, wherein when said Sequence_Header information is predicted, the number of pixels in the horizontal direction of a picture plane is predicted from information in a macroblock.
 8. A video processing apparatus according to claim 5, wherein when said Sequence Header information is predicted, the number of pixels in the vertical direction of a picture plane is predicted from information in a slice, the number of pixels in the horizontal direction of the picture plane is predicted from said number of pixels in the vertical direction and said number of pixels in the horizontal direction and an aspect ratio of the picture plane is predicted. 